1. Field of the Invention
The present invention relates generally to digital memory systems and, more particularly, to methods and systems for reading data stored in a memory cell.
2. Description of the Related Art
Memory systems typically include an array of separate memory cells. Each memory cell stores one data bit (i.e., a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d state). In an EPROM such as an EEPROM, a flash EPROM, or a flash EEPROM, the data stored in each memory cell must be verified. One method of verifying the contents of the data stored in each memory cell is to compare a cell output voltage of the memory cell to a reference output voltage of a reference cell. The reference cell voltage may be the equivalent of a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d state. The cell output voltage is compared to the reference output voltage. If the cell output voltage is the same as the reference output voltage, then the memory cell is verified as having the same state as the reference cell. The state of the memory cell is then compared to the data that is intended to be stored in the memory cell. If the memory cell has the correct state, then a next memory cell is similarly tested. If the memory cell does not have the correct state, then the memory cell must be reprogrammed.
One of the problems of the above process is that, as semiconductor device structures have become smaller, the speeds of the devices have increased, and the operating voltages have been reduced. For example, in many early generations of semiconductor devices, a xe2x80x9c1xe2x80x9d state was represented by a 5 VDC output voltage and a xe2x80x9c0xe2x80x9d state was represented by a 0 VDC (i.e., ground) output voltage. In more recent device structures a xe2x80x9c1xe2x80x9d state has been represented by a 1 VDC or even less (e.g., 0.6 VDC) output voltage, while a xe2x80x9c0xe2x80x9d state still has been represented by a 0 VDC (e.g., ground) output voltage. Further, the 0 VDC can often be slightly above ground potential such as 0.1 VDC. As the voltage difference between a xe2x80x9c1xe2x80x9d state and a xe2x80x9c0xe2x80x9d state has decreased, the process of determining whether a given device is in a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d state becomes more finite and typically slower. The process has become more finite because the voltage difference is small (e.g., less than 1 VDC) and therefore requires very specific measurement. Because the process is more finite and because the voltage is so small, the process also has become slower. The output voltage typically must be allowed to rise to a near maximum voltage before the output voltage can be accurately measured.
FIG. 1 is a schematic diagram of a prior art circuit 100 for comparing a single reference cell 20 to a memory cell 10. The memory cell 10 generates a memory cell current when a gate potential is applied to the memory cell""s word line. The memory cell current is compared to a current from a reference cell 20 by the comparator 30. Typically, EPROMs employ a column of UV-erased cells, which are identical in structure to the memory cells and act as the reference cells. The comparator 30 determines whether the memory cell 10 being verified is drawing more or less current than the reference cell 20, which is weighted in some relationship to the memory cell 10. In doing so, the comparator 30 verifies the program state of the memory cell 10.
As both the memory cell 10 and the reference cell 20 of the typical EPROM are UV-erased, each has a different distribution of currents. Normally, this difference in distribution prevents the currents from being compared directly because of the possibility that an erased memory cell being verified could appear to be programmed and vice versa. To resolve this problem, a resistive load (such as Rref) is used to effectively divide or weight the reference current, Iref. The typical load used is one-half or one-third that of the load Rcel for the memory cell 10, resulting in a 2 to 1 or 3 to 1 load ratio. Currents also have been compared using other load ratios.
In FIG. 1, memory cell 10 is a transistor that represents a typical array memory cell such as in a xe2x80x9cflashxe2x80x9d EPROM. The memory cell 10 is coupled to a positive input 31 of comparator 30 via line 41. A potential applied to the gate of memory cell 10 puts the cell into conduction, provided the potential is greater than the cell""s threshold potential, Vt1(cel). Reference cell 20 is the reference cell for memory cell 10 and is used to produce a reference current, Iref, which is used to determine the presence of a charge in the memory cell 10. The reference cell 20 is coupled to the negative input 32 of comparator 30 via line 42. A potential applied to the gate of reference cell 20 puts the reference cell into conduction if the potential is greater than its threshold potential, Vt1(ref). When the program state of memory cell 10 is being verified, a gate potential, VWL1(cel), is applied to the memory cell 10 and a gate potential, VWL1(ref), is applied to reference cell 20 to produce a memory cell current, Icel, and a reference cell current, Iref, respectively. When currents Icel and Iref are conducting, array side load resistance Rcel 11 and reference cell side load resistance Rref 21 create voltages V+ and Vxe2x88x92, respectively. Voltages V+ and Vxe2x88x92 represent the input voltages to comparator 30.
If both cells 10 and 20 are conducting, then the input voltages to comparator 30 are depicted by the following approximate or first order equations:
The output signal of the comparator 30, CPout, changes state or xe2x80x9ctripsxe2x80x9d when:
As described above, the comparator 30 amplifies the difference between the V+ and Vxe2x88x92. If the memory cell 10 is conducting and the reference cell 20 is not conducting, then the difference output from the comparator 30 can still be quite small and therefore slow to change state. As a result, verifying each of the many thousands of memory cells in an entire programmed memory array will require an excessive amount of time.
Therefore, in view of the foregoing, what is needed is a method and apparatus for quickly and accurately verifying the programmed state of each memory cell in a programmed memory array.
Broadly speaking, the present invention fills these needs by using dual reference cells to read or verify data in a memory cell. By way of example, the present invention may be implemented in the form of a system, an apparatus, a method, a device, or a computer readable media.
In accordance with one aspect of the present invention, a system for reading data in a memory cell is provided. This system includes first, second, and third comparators, each of which has a first input and a second input. A first reference cell having a low reference voltage is coupled to the first input of the first comparator. A second reference cell having a high reference voltage is coupled to the first input of the second comparator. A memory cell having a memory cell voltage is coupled to the second input of both the first comparator and also the second comparator. The first input of the third comparator is coupled to an output signal of the first comparator, which includes a difference voltage between the memory cell voltage and the low reference voltage. The second input of the third comparator is coupled to an output signal of the second comparator, which includes a difference voltage between the memory cell voltage and the high reference voltage.
In one embodiment, the output signal of the third comparator is a representation of data stored in the memory cell. In one embodiment, the low reference voltage is substantially equal to the memory cell voltage when the memory cell is in a low voltage state. In one embodiment, the high reference voltage is substantially equal to the memory cell voltage when the memory cell is in a high voltage state. In one embodiment, the first reference cell is coupled to ground such that the low reference voltage is substantially equal to the ground potential. In one embodiment, the first reference cell includes a first voltage divider circuit and the second reference cell includes a second voltage divider circuit.
In accordance with another aspect of the present invention, an apparatus for reading data contained in a memory cell is provided. This apparatus includes a first reference cell having a high threshold voltage for providing a low reference current. A second reference cell having a low threshold voltage provides a high reference current. A first load receives the high reference current and outputs a first reference voltage. A second load receives the low reference current and outputs a second reference voltage. A first comparator receives the first reference voltage and a memory cell voltage and generates an output signal. A second comparator receives the second reference voltage and the memory cell voltage and generates an output signal. A third comparator receives the output signals from the first and second comparators and generates an output signal.
In one embodiment, the output signal from the third comparator represents data contained in the memory cell. In one embodiment, the first and second loads include at least one resistor. In one embodiment, the first and second loads include at least one capacitor.
In accordance with yet another aspect of the present invention, a method for reading data in a memory cell is provided. In this method a first reference cell voltage is compared with a memory cell voltage from a memory cell to produce a first output signal. A second reference cell voltage is compared with the memory cell voltage to produce a second output signal. The first output signal is then compared with the second output signal to produce a third output signal.
In one embodiment, the first reference cell is a low reference voltage and the second reference cell is a high reference voltage. In one embodiment, the low reference voltage is substantially equal to the memory cell voltage when the memory cell is in a low voltage state. In one embodiment, the low reference voltage is substantially equal to a ground potential. In one embodiment, the third output signal is a representation of data in the memory cell. In one embodiment, the first reference cell includes a first voltage divider circuit and the second reference cell includes a second voltage divider circuit.
One advantage of the present invention is that the representation of the stored data is amplified by combining the differences between the memory cell state and both a reference xe2x80x9c1xe2x80x9d state and also a reference xe2x80x9c0xe2x80x9d state. The resulting representation of the stored data can be detected more accurately and more quickly than in conventional systems and methods that use only a single reference cell.